In recent years, a stacked semiconductor memory device has been proposed in which memory cells are integrated three-dimensionally. In such a stacked semiconductor memory device, a stacked body in which electrode films and insulating films are stacked alternately is provided on the semiconductor substrate; and semiconductor pillars that pierce the stacked body are provided. Thereby, memory cell transistors are formed at each crossing portion between the electrode films and the semiconductor pillars. On the other hand, transistors that switch between whether or not potentials are supplied to the electrode films are provided at the periphery of the stacked body. The end portion of the stacked body is patterned into a staircase configuration; a contact is connected to each of the electrode films; and the contacts are connected to the transistors via upper layer interconnects. In such a semiconductor memory device, when the number of stacks of electrode films increases, the number of upper layer interconnects increases; and it becomes difficult to make the layout.